The present invention relates to an ESD protecting circuit in integrated circuits, and more specifically, to an gate-coupled ESD protecting circuit without transient leakage in integrated circuits.
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. As the size of the devices is scaled down, the ESD (electrostatic discharge) damage has become one of the main reliability concerns on the IC (integrated circuit) products. Especially, while the CMOS technology is developed into the deepsubmicron regime, the scaled-down MOS devices and thinner gate oxide become more vulnerable to ESD stress. For general industrial specification, the input and output pins of the IC products have to sustain the ESD stress of above 2000 Volts. Therefore, the ESD protection circuits have to be placed around the input and output pads of the IC""s to protect the IC""s against the ESD damage.
Please referring to FIG. 1, A typical input ESD protection circuit according to a prior art is shown. The ESD protection circuit includes a gate-grounded NMOS Mn1 with a larger device dimension for protecting the input circuits of the IC. The internal circuits 100 is protected by the ESD protective circuit. A power line VDD and a power line VSS are coupled to the internal circuits 100 and indicated as the power supplies of the internal circuits 100. An input pad 10 is coupled to the drain of the NMOS Mn1, and coupled to the internal circuits 100 through a resistor R. The gate and source of the NMOS Mn1 are coupled to the power line VSS. In order to sustain a high ESD current, the gate-grounded NMOS (often called as GGNMOS) Mn1 in FIG. 1 is drawn with a huge device dimension, such as W/L=500/0.5 in a typical 0.35 xcexcm CMOS technology. With such a huge device dimension, the GGNMOS Mn1 is typically drawn with 10-fingers poly gates [1]. However, the GGNMOS with a large layout area and a huge device dimension had been found that the GGNMOS just sustains a low ESD voltage, because the multiple poly gates of the GGNMOS can not be uniformly turned-on during the ESD stress [2]. Only few poly gates in the layout of the large-dimension GGNMOS are turned-on to bypass the ESD current, but most of the other poly gates still keep off during the ESD stress. Only few poly gates of the large-dimension GGNMOS are turned on to bypass the ESD current, therefore the large-dimension GGNMOS can only sustain a low ESD level. In order to improve the ESD level of such large-dimension GGNMOS, the multiple poly-gate fingers of the large-dimension GGNMOS have to be uniformly triggered on to share ESD-stress current. If all the poly gates of the large-dimension GGNMOS can be uniformly turned-on during the ESD-stress condition, the large dimension GGNMOS can sustain a much high ESD level [2].
[1] S. G. Beebe, xe2x80x9cMethodology for layout design and optimization of ESD protection transistors,xe2x80x9d 1996 EOS/ESD Symp. Proc., pp. 265-275.
[2] T. L. Polgreen and A. Chatterjee, xe2x80x9cImproving the ESD failure threshold of silicided NMOS output transistors by ensuring uniform current flow,xe2x80x9d IEEE Trans. Electron Devices, vol.39,pp. 379-388,1992.
To achieve the uniform turn-on behavior among the multiple poly-gate fingers of the large-dimension NMOS, a gate-coupled technique had been reported to improve the ESD level of the large-dimension NMOS [3]-[9]. The typical gate-coupled design for input ESD protection circuit is shown in FIG. 2, wherein a capacitor Cn is connected from the input pad 10 to the gate of the ESD protection NMOS Mn1, and the gate of the NMOS Mn1 is connected to the power line VSS through a resistor Rn. Such a gate-coupled NMOS Mn1 has been called as GCNMOS [5]-[7]. The capacitor Cn is used to couple the ESD transient voltage from the input pad 10 to the gate of the NMOS Mn1. With a coupled voltage on the gate of the NMOS Mn1, all the poly gates of the large-dimension NMOS can be uniformly turned on to bypass the ESD current. Therefore, the ESD level of the large-dimension NMOS can be effectively improved. To sustain the coupled voltage on the gate of the NMOS Mn1, the resistor Rn is added from the gate of NMOS Mn1 to VSS. When the ESD-transient voltage is coupled through the Cn to the gate of NMOS Mn1, such coupled voltage held longer in time by the resistor Rn. So, the NMOS Mn1 can be efficiently triggered on to bypass the ESD current.
Please referring to FIG. 3, the operating waveforms in the time domain according to the traditional gate-coupled (GCNMOS)design are illustrated. The human-body-model ESD voltage pulse 310 has a rise time around 5-15 ns. While such ESD voltage pulse 310 is attached to the input pad 10, the rising edge of the ESD voltage pulse 310 generates the displacement current through the Cn (referring to FIG. 2) to the gate of the NMOS Mn1. The coupled voltage on the gate of the NMOS Mn1 will be discharged by the resistor Rn to VSS. Therefore, the gate voltage Vg has a voltage waveform as shown in FIG. 3. The time period, when the Vg is greater than the threshold voltage (Vth) of the NMOS Mn1, is the turn-on time (ton) of the GCNMOS. The larger Cn and larger Rn lead to a longer turn-on time of the GCNMOS in the ESD protection circuit [8]. So, the gate-couple technique can effectively improve the ESD level of the large-dimension NMOS in the ESD protection circuit.
An alternative design of the gate-coupled ESD protection circuit is shown in FIG. 4 [8]-[9], wherein the gate-coupled technique is applied to both the NMOS and PMOS devices in the input ESD protection circuit to achieve the uniformly turn-on behavior among the multiple fingers of the ESD-protection devices. The gate-coupled circuits about the PMOS devices are same as those of the NMOS devices. A capacitor Cp is connected from the input pad 10 to the gate of the ESD-protection PMOS Mp1, and the gate of the PMOS Mp1 is connected to the power line VDD through a resistor Rp. [3] C. Duvvury and R. N. Rountree, xe2x80x9cOutput buffer. with improved ESD protection,xe2x80x9d U.S. Pat. No. 4,855,620, August 1989.
[4] C. D. Lien, xe2x80x9cElectrostatic discharge protection circuit,xe2x80x9d U.S. Pat. No.5,086,365, February 1992.
[5] C. Duvvury and C. Diaz, xe2x80x9cDynamic gate coupling of NMOS for efficient output ESD protection,xe2x80x9d Proc. of IRPS, 1992, pp.141-150.
[6] C. Duvvury, C. Diaz, and T. Haddock, xe2x80x9cAchieving uniform NMOS device power distribution for submicron ESD reliability,xe2x80x9d in Tech. Dig. IEDM, 1992, pp.131-134.
[7] S. Ramaswamy, C. Duvvury, and S. M. Kang, xe2x80x9cEOS/ESD reliability of deep sub-micron NMOS protection devices,xe2x80x9d in Proc. of IRPS, 1995, pp.284-291.
[8] M. D. Ker, C. Y. Wu, T. Cheng, and H. H. Chang, xe2x80x9cCapacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC,xe2x80x9d IEEE Trans. on VLSI Systems, vol.4, pp.307-321, September 1996.
[9] M. D. Ker, C. Y. Wu, T. Cheng, C. N. Wu and T. L. Yu, xe2x80x9cCapacitor-couple electrostatic discharge protection circuit,xe2x80x9d U.S. Pat. No. 5,631,793, May. 1997.
The gate-coupled design can improve the ESD level of the ESD-protection devices with large device dimensions. Referring to FIG. 3, the larger Cn will generate higher coupled voltage on the gate of the NMOS Mn1 to uniformly turn on the NMOS Mn1 to bypass ESD current. However, the NMOS Mn1 should be kept off when the IC is in the normal operating conditions. In the normal operating conditions, the input signal is applied to the input pad 10 from other IC""s or circuits. The input signal may have a sharp rising edge for high-speed applications. For example, the rise time of the input signal may has a rise time of 1 ns for the input signal with 100 MHz operating frequency. For faster operating speed, the rise time of the input signal will become shorter. In such high-speed applications, the sharp rising edge (dV/dt) of the input signal may generate a displacement current of Ic=Cnxc3x97(dV/dt) through the Cn to the gate of the ESD-protection device NMOS Mn1. Thus, the gate voltage of the NMOS Mn1 in such high-speed applications may be coupled with a transient voltage greater than its threshold voltage.
Please referring to FIG. 5A, the typical voltage waveforms of the input signal and the coupled voltage on the gate of the NMOS Mn1 are shown. Because the gate of NMOS Mn1 is coupled with a transient voltage Vg greater than its threshold voltage Vth, the NMOS Mn1 is turned on and generates a leakage current path from the input pad 10 to the power line VSS. Because the NMOS Mn1 is designed for ESD protection, such a NMOS Mn1 is drawn with a large device dimension to sustain the high ESD-current stress. The large-dimension NMOS Mn1 is turned on by the high-speed input signal with a sharp rising edge, so the input signal will be seriously degraded by the turned-on NMOS Mn1. A typical waveform of the input signal degraded due to the turned-on NMOS Mn1 is shown in FIG. 5B, wherein the sharp rising edge of the input signal is degraded by the leakage current through the NMOS Mn1. The recess curve A illustrates the degraded portion of the input signal.
The ESD-protection device NMOS Mn1 in the IC normal operating conditions should be kept off. However, using the gate-couple technique to improve the ESD level of the NMOS Mn1, the couple capacitor Cn is added to the gate of NMOS Mn1 to uniformly trigger on the large-dimension NMOS Mn1 for effective ESD protection. But, such an ESD-coupled capacitor Cn can also couple the input signal with sharp rising edge to turn on the NMOS Mn1 when the IC is in the normal operating conditions. The causes the input waveform with serious degradation. So The effective gate-couple design for ESD protection is not suitable for applying in the IC""s with high-speed operations.
In this invention, a solution has been proposed to overcome the aforementioned problem in prior art. This invention proposes a practical solution to successfully and safely apply the gate-coupled technique for ESD protection in the IC""s with high-speed input signals, but without causing the transient leakage in the ESD protection circuit when the IC""s is in the normal operating conditions.
An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD) comprises an internal circuit coupled with the first power line and the second power line, and an input pad coupled to the internal circuit for inputting signals to the internal circuit. A first voltage clamp circuit is coupled to the first power line for clamp potential level through the first voltage clamp circuit. A first voltage bypass circuit is coupled to the first voltage clamp circuit and a second power line for biasing the first voltage clamp circuit to the second power line, wherein the first voltage bypass circuit and first voltage clamp circuit are both coupled with the internal circuit and coupled to the input pad. A second voltage clamp circuit is coupled to a second, power line for clamp potential level through the second voltage clamp circuit, and a second voltage bypass circuit is coupled to the second voltage clamp circuit and the first power line for biasing the second voltage clamp circuit to the first power line, wherein the second voltage bypass circuit and second voltage clamp circuit are both coupled with the input pad and coupled to the internal circuit.